Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.
For all of these PLDs, the functionality of the device is controlled by data bits (the “configuration bitstream”) provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
PLD designs can include millions of logic gates, and therefore can be very complicated. Hence, a common method of designing for a PLD includes incorporating pre-developed logic blocks (“cores”) into the design. A core can include a predetermined set of configuration bits that program the PLD to perform one or more functions. Alternatively, a core can include source code or schematics that describe the logic and connectivity of a design. Typical cores can provide, but are not limited to, digital signal processing (DSP) functions, memories, storage elements, and math functions. Some cores include an optimally floorplanned layout targeted to a specific family of PLDs. Cores can also be parameterizable, i.e., allowing the user to enter parameters to activate or change certain core functionality.
Developers of PLD applications are becoming increasingly reliant on outside core developers or “IP (intellectual property) providers” for components of their systems. In some sensitive applications, developers may be concerned that an IP provider could include in a core additional logic designed to monitor or even interfere with the functionality of the design. To provide one simple example, a PLD design used in a ATM (automatic teller machine) system could include in one of its cores “Trojan horse” logic that allows a specific cardholder to withdraw cash from an account without reporting the transaction to the bank.
Therefore, it is desirable to provide methods by which PLD designers can confirm that no such unwanted logic has been inserted into their designs.